[FPGA] FND_Counter 리셋 추가 구현

counter_10000v

`timescale 1ns / 1ps

module counter_10000(
    input i_rst_sw,
    input i_100hz_clk,
    output [13:0] o_fndCnt
    );

    reg [13:0] r_fndCnt = 0;

    always @(posedge i_100hz_clk or negedge i_rst_sw ) begin
    if (i_rst_sw == 0)
        r_fndCnt = 0;
    else
        r_fndCnt <= (r_fndCnt+1) % 10000;
    end