[FPGA] cnt4 출력값 7-segment LED에 표시하기

cnt4v2.v

module cnt4v2(
    input rst, clk,
    output reg [3:0] qout,
    output wire [6:0] segd
    );
   
    
    always @(negedge rst or posedge clk)
        if (rst == 0) 
        qout <= 0;
        else
        qout <= qout + 1 ;
    assign segd = (qout == 4'h0)? (7'b011_1111) :
                  (qout == 4'h1)? (7'b000_0110) :
                  (qout == 4'h2)? (7'b101_1011) :
                  (qout == 4'h3)? (7'b100_1111) :
                  (qout == 4'h4)? (7'b110_0110) :
                  (qout == 4'h5)? (7'b110_1101) :
                  (qout == 4'h6)? (7'b111_1101) :
                  (qout == 4'h7)? (7'b000_0111) :
                  (qout == 4'h8)? (7'b111_1111) : 
                  (qout == 4'h9)? (7'b110_1111) :
                  (qout == 4'ha)? (7'b101_1111) :
                  (qout == 4'hb)? (7'b111_1100) :
                  (qout == 4'hc)? (7'b011_1001) :
                  (qout == 4'hd)? (7'b101_1110) :
                  (qout == 4'he)? (7'b111_1001) :
                  (qout == 4'hf)? (7'b111_0001) :
                                  (7'b000_0001) ;
        endmodule

cnt4v2_tb.v

module cnt4v2_tb(
   
    );
    reg rst, clk;
    wire [3:0] qout;
    wire [6:0] segd;
    cnt4v2 u_cnt4v2( 
        .rst(rst), .clk(clk), .qout(qout) , .segd(segd));
     
      initial begin
      rst = 1;  clk = 0;
       # 100 rst = 0;
       # 200 rst = 1;
     
     
     
      end
      always clk=#50 ~clk;
endmodule

cnt4v2.xdc

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN T16} [get_ports rst]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN Y16} [get_ports clk]

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN D18} [get_ports qout[3]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN G14} [get_ports qout[2]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN M15} [get_ports qout[1]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN M14} [get_ports qout[0]]

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN T20} [get_ports segd[0]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN U20} [get_ports segd[1]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN V20} [get_ports segd[2]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN W20} [get_ports segd[3]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN Y18} [get_ports segd[4]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN Y19} [get_ports segd[5]]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN W18} [get_ports segd[6]]


set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]