[FPGA] cnt_priority 설계

cnt_priority.v

module cnt_priority(
    input rst, clk,
    input cen, clr,
    input ld,up_dn,
    input [7:0] ldv,
    output reg [7:0] qout
    );
   
    
    always @(negedge  rst or posedge clk)
    begin
        if (rst == 0) 
            qout <= 0;
        else
            if (cen == 0)
                qout <= qout;
                else if (clr == 1)
                    qout <= 0;
                else if (ld == 1)
                    qout <= ldv;
                else if (up_dn == 1)
                    if (qout >= 199)
                    qout <= 0;
                    else
                        qout <= qout + 1;
                else
                    if ((qout == 0 ) | (qout > 199))
                        qout <= 199;
                    else
                        qout <= qout - 1;
end
endmodule

cnt_priority_tb

module cnt_priority_tb();
    reg rst, clk, cen, clr, ld, up_dn;
    reg [7:0] ldv;
    wire [7:0] qout;
    
    cnt_priority u_cnt_priority(
        .rst (rst), .clk (clk), .cen (cen), .clr (clr), .ld (ld), .up_dn (up_dn), .ldv (ldv), .qout (qout)
    );
    
    initial begin
        rst = 0; 
        clk = 0; 
        cen = 0; 
        clr = 0; 
        ld = 0; 
        up_dn = 1; 
        ldv = 10;
        
        #50 rst = 1;
        #50 cen = 1;
        #50 cen = 0;
        #50 cen = 1;
        #200 clr = 1;
        #50 clr = 0;
        #200 ld = 1;
        #50 ld = 0;
        #500 up_dn = 0;
    end
    
    always clk = #50 ~clk;
     
endmodule

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