[FPGA] Stopwatch + Clock + LED bar

TOP

module top_timeWatch(
    input sysclk,
    input i_rst_n,
    input i_mode,
    output o_muxOut_2,
    output [3:0] o_fndSelect,
    output [7:0] o_fndFont
    );

    wire w_sec_ind;
    
    TimeClock timer(
        .sysclk(sysclk),
        .i_rst_n(i_rst_n),
        .o_sec_ind(w_sec_ind),
        .o_timeData(w_timeData)
    );
    
    wire [13:0] w_timeData;
    wire w_upc_ind;
    
    upCounter upcount(
        .sysclk(sysclk),
        .i_rst_n(i_rst_n),
        .o_upc_ind(w_upc_ind),
        .o_upCounter(w_upcounter)
    );

    wire [13:0] w_upcounter;

    MUX muxs(
        .i_mode(i_mode),
        .i_timer(w_timeData),
        .i_upcounter(w_upcounter),
        .o_muxOut(w_muxOut)
    );
    
    MUX_2 muxs_2(
        .i_mode(i_mode),
        .i_sec_ind(w_sec_ind),
        .i_upc_ind(w_upc_ind),
        .o_muxOut_2(o_muxOut_2)
    );

    wire [13:0] w_muxOut;

    FND_Display fndDisplay(
        .sysclk(sysclk),
        .i_rst_n(i_rst_n),
        .i_fndData(w_muxOut),
        .o_fndSelect(o_fndSelect),
        .o_fndFont(o_fndFont)
    );

endmodule