[FPGA] Watch + Fan + FND 구현

TOP

module top_watch_fan(
    input sysclk,
    input i_rst_n,
    input [1:0]i_sw,
    input i_mode,
    
    output o_pwm_out,
    output [3:0]o_fndSelect,
    output [7:0]o_fndFont
    );
    
    TOP_PWM_Generator pwm_generator(
    .sysclk(sysclk),
    .i_rst_n(i_rst_n),
    .i_sw(i_sw),
    .o_pwm_out(o_pwm_out),
    .o_pwm_to_fnd(w_pwm_to_fnd)
     );
     wire [13:0] w_pwm_to_fnd;
     
     top_Time_Clock time_clock(
    .sysclk(sysclk),
    .i_rst_n(i_rst_n),
    .o_time_data(w_time_data),
    .o_led(o_led)
    );
    wire [13:0] w_time_data;
    
    MUX mux(
    .i_mode(i_mode),
    .i_pwm_to_fnd(w_pwm_to_fnd),
    .i_time_data(w_time_data),
    .o_muxOut(w_muxOut)
    ); 
    wire [13:0]w_muxOut;
    
    FND_Display fnd_display(
    .sysclk(sysclk),
    .i_rst_n(i_rst_n),
    .i_fndData(w_muxOut),
    .o_fndSelect(o_fndSelect),
    .o_fndFont(o_fndFont)
    );
endmodule