[FPGA] mux4b 설계

교재 74P의 mux4b참조

mux4b.v

`timescale 1ns / 1ps
module mox4b(
    input [3:0] d0, d1, d2, d3,
    input [1:0] sel,
    output[3:0] y
    );
    
    assign y =  (sel == 0) ? d0 :
                (sel == 1) ? d1 :
                (sel == 2) ? d2 :
                d3;
    
endmodule

mux4b_tb.v

`timescale 1ns / 1ps
module mox4b_tb(
    );
    reg [3:0] d0, d1, d2, d3;
    reg [1:0] sel;
    wire [3:0] y;
    
    mox4b u_mox4b (       
    .d0(d0), .d1(d1), .d2(d2), .d3(d3), .sel(sel), .y(y));
    
    initial begin // 초기화
        d0 = 4'b0;   
        d1 = 4'b0; 
        d2 = 4'b0; 
        d3 = 4'b0;  
        sel = 0;
        end 
       always d0 = #100 ~d0;
       always d0 = #200 ~d1;
  	   always d0 = #300 ~d2;
       always d0 = #400 ~d3;
       always sel[0] = #1000 ~sel[0];
       always sel[1] = #2000 ~sel[1];
endmodule